邓伟

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邓伟 准聘副教授


电子邮箱:wdeng@tsinghua.edu.cn

电话:+86-10-62792712

地址:北京市清华大学东主楼9区小二楼


Wei Deng, Associate Professor

Email:wdeng@tsinghua.edu.cn

Phone: +86-10-62792712

Address: Second Floor, Zone 9, East main building, Tsinghua University







邓伟,副教授,博士生导师。2002-2009年在电子科技大学电子工程系并先后获得学士和硕士学位;2009-2014年在日本东京工业大学(Tokyo Institute of Technology)先后获得博士学位和从事博士后研究;2015-2019年在美国苹果公司(Apple Inc.)总部任高级主任工程师,面向无线通信SoC和A系列处理器SoC从事射频、毫米波和混合信号芯片的研发。2019年起到清华大学集成电路学院工作。

邓伟副教授长期从事射频、毫米波和太赫兹芯片设计与系统集成,主持国家自然科学基金重点项目、国家重点研发计划课题等一系列国家科技项目。现任ISSCCVLSI和ESSCIRC的技术委员会成员以及IEEE SSC-L期刊副主编,负责射频和无线方向。在JSSC、IEEE T-CAS I/II等期刊以及ISSCC、VLSI等国际会议发表论文100余篇,其中在JSSCISSCC发表论文20余篇,申请和授权发明专利20余项。获得过IEEE SSCS Predoctoral Achievement Award、Tejima Research Award和IEEE/ACM ASP-DAC Best Design Award等奖项。


招生/招聘信息:本课题组每年招收3-4名博士/硕士研究生,常年招聘硅基射频、毫米波和太赫兹芯片设计与系统集成等方向的博士后,同时也非常欢迎感兴趣的本科生参与科研。详情请附上简历咨询wdeng@tsinghua.edu.cn.


主要研究方向:

1. 硅基射频、毫米波和太赫兹无线通信收发机芯片设计与系统集成

2. 硅基毫米波和太赫兹感知收发机芯片设计与系统集成


Prof. Wei Deng is currently an Associate Professor with the School of Integrated Circuits at Tsinghua University, Beijing, China. He received the B.S. and M.S. degrees in electronic engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Tokyo, Japan, in 2013. From 2013 to 2014, he was a Post-Doctoral Researcher with the Tokyo Institute of Technology. From 2015 to 2019, he was with Apple Inc., Cupertino, CA, USA, working on radio frequency (RF), millimeter-wave (mm-wave), and mixed-signal IC design for wireless transceivers and Apple A-series processors. Since 2019, he has been a Faculty Member with the School of Integrated Circuits, Tsinghua University, Beijing, China. He has authored or co-authored over 100 IEEE journal and conference articles including over 20 ISSCC and JSSC. He holds/filed 20 patents. His research interests include RF; mm-wave; terahertz; and mixed-signal integrated circuits and system for wireless communications, sensing, and imaging systems. Dr. Deng currently serves as a Technical Program Committee Member for ISSCC, VLSI, and ESSCIRC. He has been an Associate Editor of the IEEE Solid-State Circuits Letters (SSC-L).  He has been PI of several research projects funded by MOST and leading global companies. He was a recipient of several national and international awards, including the IEEE SSCS Predoctoral Achievement Award, the Tejima Research Award, and the IEEE/ACM ASP-DAC Best Design Award.


Group Openings: Our group has openings for 3-4 PhD/Master students every year and regularly recruit postdocs with related background in RF, mm-wave, THz and mixed-signal integrated circuits and system design. Undergraduate students are also encouraged to participate in our research. For more information, please email mailto:wdeng@tsinghua.edu.cnwith your CV.


Major Professional Activities and Service主要学术兼职

· International Solid-State Circuits Conference (ISSCC), Technical Program Committee (TPC) Member

· IEEE Solid-State Circuits Letters (SSC-L), Associate Editor

· IEEE Symposia on VLSI Technology and Circuits (VLSI), Technical Program Committee (TPC) Member

· IEEE European Solid-State Circuits Conference (ESSCIRC), Technical Program Committee (TPC) Member


Major Publications 代表性学术论文

[1] Z. Chen, W. Deng, H. Jia, P. Guan, T. Ma, S. Sun, X. Huang, G. Chen, R. Ma, S. Dong, L. Duan, Z. Wang, and B. Chi, A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS,” IEEE Symposium on VLSI Circuits (VLSI Circuits), June 2021.

[2] W. Deng, Z. Chen, H. Jia, S. Sun. G. Chen. Z. Wang, and B. Chi, “A 11.1-to-14.2 GHz Self-Adapted Two-Point Modulation Dual-Path Type-II Digital PLL Concurrently Achieving 124.7-MHz/ μs Chirp Rate and 2.27-GHz Bandwidth,” IEEE Symposium on VLSI Circuits (VLSI Circuits), June 2021.

[3] H. Jia, W. Deng, P. Guan, Z. Wang, and B. Chi,“A 60 GHz 186.5 dBc/Hz FOM Quad-Core Fundamental VCO using Circular-Triple-Coupled-Transformer with No Mode Ambiguity in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.

[4] W. Deng, Z. Song, R. Ma, J. Lin, J. Ye, S. Kong, S. Hu, H. Jia, and B. Chi, "An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver with Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 8, pp. 2027-2042, Aug. 2020

[5] T. Ma, W. Deng, Z. Chen, J. Wu, W. Zheng, S. Wang, N. Qi, Y. Liu, B. Chi, "A CMOS 76-81 GHz 2TX/3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 2, pp. 233-248, Feb. 2020

[6] J. Wu, W. Deng, Z. Chen, W. Zheng, Y. Liu, S. Wang, N. Qi, B. Chi, "A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase Detector," IEEE Transactions on Circuits and Systems I: Regular Papers (T-CAS I), vol. 67, no. 1, pp. 60-73, Jan. 2020.

[7] H.Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019. (Invited paper)

[8] H.Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019. (Invited to JSSC

[9] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, and K. Okada, "A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. Invited paper)

[10] H. Liu, Z.Sun, D. Tang, H. Huang, T.Kaneko, Z. Chen, W. Deng, R. Wu and K. Okada, "A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,"  IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. (Invited paper)

[11] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, K. Okada, and A. Matsuzawa, "A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS,"  IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. (Invited to JSSC

[12] H. Liu, Z. Sun, D. Tang, H. Huang, T. Kaneko, W. Deng, R. Wu, K. Okada, and A. Matsuzawa, "An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. (Invited to JSSC

[13] A. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K.Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -250dB," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, Jul. 2016. (Invited paper)

[14] T. Siriburanon, S.Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W. Deng, M. Miyahara, K. Okada, and A. Matsuzawa, "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No.6 , pp. 1385-1397, Jun. 2016.

[15] T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada, and A. Matsuzawa, "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.

[16] W. Deng, D. Yang, A. Narayanan, K. Nakata, T. Siriburanon, K. Okada, and A. Matsuzawa, "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 252-253, Feb. 2015.

[17] T. Siriburanon, S. Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W.Deng, M. Miyahara, K. Okada, A. Matsuzawa, "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 440-441, Feb. 2015.

[18] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A Fully Synthesizable All-Digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique," IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015. (Invited paper)

[19] W. Deng, S. Hara, A. Musa, K. Okada, and A. Matsuzawa, "A Compact and Low-power Fractionally Injection-Locked Quadrature Frequency Synthesizer using Self-Synchonized Gating Injection Technique for Software-Defined Radios,"  IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.

[20] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.266-267, Feb. 2014. (Invited to JSSC

[21] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K.Okada, and A. Matsuzawa, "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014. (Invited paper)

[22] W. Deng, T. Siriburanon, A. Musa, K. Okada, and A. Matsuzawa, "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers,"  IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, Jul. 2013. (Invited paper)

[23] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A 0.022mm2 970µW Dual-loop Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits,"  IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2013. (Invited to JSSC

[24] W. Deng, K. Okada, and A. Matsuzawa, " Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing", IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp. 429-440, Feb. 2013.