IC & System Design Research Division

 
1. Introduction
Division of Integrated Circuits and System Design is engaged with many advanced researches in the field of large scale integrated circuits, including theories, algorithms, methodologies and architectures for System on Chip (SoC) design.
 
Our division is entitled as "Electronic System and ASIC Technology Research Center" under “211 Project” and “On-line IC Design Collaboration Center”, all sponsored by Ministry of Education of China. Our laboratory features advanced IC design and testing environment with complete CAD tools.
 
In 2004, our division received Beijing Science and Technology Progress Award by successfully developing the second generation ID card ASIC chip which has been in nationwide use. In 2005, the wavelet transform chip THSCLA, the JPEG2000 decoder chip THJ2K, the digital multi-channel cochlear ASIC CI1003 and the high-speed elliptic curve cryptography ASIC THECC successfully passed the quality evaluation performed by the Ministry of Education successfully. Also, in 2007, the high-speed security chip RSA-1024 (product model: SSX41) was approved by the Office of Security Commercial Code Administration.
 
2. Staffs
Director:
Zhang Chun
Tel: (86)-(10)-62792912
Fax: (86)-(10)-62795104
 
Vice Directors:
Chi Baoyong
Tel: (86)-(10)-62795096
Fax: (86)-(10)-62795104
 
Introduction of Research Area

No
Title
Sponsor
Principal Investigator
1
Design of UHF RFID reader SOC
863 Program
Chun Zhang
2
Ultra-low-power SoC design and prototype system implementation for wireless capsule endoscope
863 Program
Hanjun Jiang
3
Ultra-low power SoC for medical endoscopy applications
863 Program
Baoyong Chi
4
Development of the key IP cores for reconfigurable RF ICs
863 Program
Fule Li
5
Design and research of visual prosthesis system using MEMS technology
863 Program
Chun Zhang
6
RF IC research for IMT-Advanced 4G wideband wireless mobile systems
03 National Key Projects
Baoyong Chi
7
Low Power SOC for Sensor Network Node
03 National Key Projects
Chun Zhang
8
Digital circuit aided research on the on-chip self-calibration techniques of RFIC
National Natural Science Fund
Baoyong Chi
9
Study on the generation of secret keys in a cryptographic hardware by the method of on-the-flying
National Natural Science Fund
Guoqiang Bai
10
Research on the architecture of information-aware multi-task processor for novel sensor applications
National Natural Science Fund
Xiangyu Li
11
Study of large integers modular multiplication algorithm and the implementation for elliptic curve cryptography chip in GF(P)
National Natural Science Fund
Shuguo Li
12
Research on robust clocking system design for low-power I/O links
International Corporation
Woogeun Rhee
13
Ultra-low power transceiver design for wireless body area network (WBAN) Applications
International Corporation
Woogeun Rhee
14
Research on high performance SoC design for real time 3D data acquisition and processing
Tsinghua Research Plan
Xiang Xie
15
Development of a CdZnTe nuclear detector readout ASIC
Department of Engineering Physics Tsinghua University
Yihe SUN and Xiangyu LI

 
1. Design of UHF RFID reader SOC
This project aims to develop UHF RFID Reader SOC according to ISO18000-6B/C standard and China radio regulation. SOC for portable applications and chipset for high performance applications are designed. RF front-end, analog baseband, digital baseband and protocol processor are integrated in the SOC for portable applications. Key technologies of verification, testing methods, reliability and quality control for mass production are also studied.
 
2. Ultra-low-power SoC Design and prototype system implementation for wireless capsule endoscope
The purpose of this project is to design an ultra-low-power (ULP) SoC and to implement a prototype system for the wireless capsule endoscope which is used for gastrointestinal examination. To make a ULP SoC supplied by a tiny coin battery, a ULP transceiver with 3Mbps TX and 64kbps RX, a wakeup receiver based on wireless energy recovery, a lossless image compressor, an application-optimized MCU, and an on-chip power management unit has been integrated in the SoC. The designed SoC and the prototype system outperforms the conventional works in terms of image resolution, frame rate and battery life.
 
3. Ultra-low power SoC chip for medical endoscopy portable base station applications
To develop the ultra-low power SoC chip for medical endoscopy applications based on the research on the key circuit techniques of ultra-low power ICs.
 
4. Development of the key IP cores for reconfigurable RF ICs
The project is trying to develop the key building blocks for multi-mode, multi-band RF transceiver for wireless communications. These blocks include a 0.2~6 GHz RF front-end for wideband receivers with features of low noise, high linearity and high dynamic range, a 0.2~6 GHz local frequency synthesizer with features of low noise and fast locking, an reconfigurable analog baseband with adjustable center frequency and bandwidth, and a configurable and digital calibrated RF PA pre-driver with features of high efficiency, high linearity, and tunable amplitude.
 
5. Design and research of visual prosthesis system using MEMS technology
This project aims to develop implantable wireless circuit stimulator for vision prosthesis. The integrated circuit is composed of wireless transceiver, digital-to-analog converter, switching matrix, circuit stimulator. It can provide multi-channel and multi-mode stimulus, fulfilling the requirement of scientific research of vision prosthesis.
 
6. RF IC research for IMT-advanced 4G wideband wireless mobile systems
To develop low cost, low power, high performance RF ICs, devices and modules for IMT-Advanced 4G wideband wireless mobile systems. The goal of the project is to provide the experimental platforms for the next generation mobile systems.
 
7. Low power SOC for sensor network node
 This project aims to develop a low cost, low power, reliable SOC for the sensor network node. The chip will integrate RF, baseband, sensor interface and low power protocol stack, support low speed communication and self-network construction. Developing platform including tool chain, demo board, driver program will be developed for evaluation and mass production.
 
8. Digital circuit aided research on the on-chip self-calibration techniques of RFIC
Along with the development of CMOS process, the mismatch between the on-chip components, process variations and non-ideal device characteristics have all worsen. What is more, there exist the inaccurate RF component models, the package parasitic effects and many other issues during the RFIC development. All these issues result in low yield of RFIC chips and long development period, and bring many big challenges to the RFIC product development. The project aims at the researches on the on-chip self-calibration techniques of RFIC circuits which includes the following topics: (1)Research on the principle and method of on-chip performance measurements of RFICs; (2)Discuss on the topology and design technique of the performance-adjustable RFICs, and research on the principle and method to on-chip adjust the RFIC performance; (3)Research on the system control technique of RFIC on-chip self-calibration loop and implement the on-chip self-calibration function of RFIC crucial performance; (4)Implement a RF IP module with on-chip self-calibration function in deep-submicro CMOS process. The project hopes to solve the great challenges of RFIC product developments in deep-submicro CMOS process and reduce the effects of various non-ideal issues on the performance of RFIC products, which could shorten the development time, improve the product yield and lower down the development cost.
 
9. Studying on the generation of secret keys in a cryptographic hardware by the method of on-the-flying
For the secret keys being in storage in a cryptographic hardware, attackers can obtain them by the method of inverse engineering. This project presented a new method of generating the secret key to prevent such attacks. According to the method, there are no secret keys being in storage but some tools to generate the keys to be presented in the cryptographic hardware. When needed, one can generate the secret key on the fly using such tools and destroys it when the mission is finished. Such generating tools will definitely been destroyed when one does inverse engineering for the cryptographic hardware. As this, the attacker can neither obtain the secret key, nor the generating tools by the method of inverse engineering.
 
10. Research on the architecture of information-aware multi-task processor for novel sensor applications
Oriented to energy-harvesting high performance sensor embedded applications, this project explores the architecture of multi-task processor with information-aware as its central task. This kind of processors performs task scheduling, power management, configuration and so on according to the input signals and the energy supporting situation adaptively with a uniform mechanism. It is expected to improve the multi-channel embedded information acquisition system’s efficiency, which is insufficient to handle a huge number of data due to the overhead about multiple heterogeneous tasks management as well as the uncertainty of environment factors and input data. Its research content covers the task scheduling and power management methods, architecture and the key implementation techniques under multi-task and energy-harvesting conditions.
 
11. The study of large integers modular multiplication algorithm and the implementation for elliptic curve cryptography chip in GF(P)  
The speed of the chip can be determined by the modular multiplication algorithm. This project will present an algorithm of modular multiplication for large integers and a design method for the large integers multiplier, and finish the chip fabrication for elliptic curve cryptography in GF(P) with the multiplier.
 
12. Research on robust clocking system design for low-power I/O links
For low-cost serial I/O links, low-power but robust clocking system design is essential. In addition to clock speed, the use of advanced CMOS technologies makes it more challenging to design robust clocking systems due to low supply voltage, on-chip variability, modeling inaccuracy, and gate leakage current effect. Increased uncertainty in the modeling of the passive devices and transistors mandates conservative IC designs to function beyond original targets in order to provide enough performance margin over process, voltage, and temperature (PVT) variations. In this project, we work on a technology-friendly low power clocking system design with robust performance for high speed serial I/O links.
 
13. Ultra-low power transceiver design for wireless body area network (WBAN) applications
With the rapid development of wireless communication technologies, health-care monitoring systems have recently received significant attention. Ultra-wideband (UWB) systems have shown promising features for short range and low data rate wireless applications because of high power efficiency, good coexistence with other wireless standards, high range resolution, very low radiated power, high penetration capability, and good interference resilience. This project is toward building an ultra-low power low data rate transceiver for upcoming IEEE 802.15.6 standard, the architecture of which can be reconfigurable and extended to general WBAN and WPAN applications.
 
14. Research on high performance SoC design for real time 3D data acquisition and processing
With the development of 3D image data acquisition and display technologies, it is an inevitable trend that the 2D images will be replaced by 3D images in future work, life and technology fields. Actually, many kinds of devices based on 3D technologies spring up in recent years, such as networking appliance, portable 3D data acquisition equipment and so on. Furthermore, research on 3D technologies gradually becomes an emphasis. For device miniaturization and low power consumption in 3D applications, our project is engaged with core technologies in high performance SoC, including real time pre-processing on 3D data (image rectification, multiple-view images matching and color correction), real time 3D representation and coding and parallel processing on 3D data with low power consumption. This subject aims at satisfying technology demands in the future 3D world to make people’s life more convenient with 3D devices and then laying a foundation for related industries development.
 
15. Development of a CdZnTe nuclear detector readout ASIC
This project is going to develop a CdZnTe nuclear detector readout ASIC. The CdZnTe detector is a kind of common nuclear signal sensor. And the ASIC to be designed is the analog front-end of a nuclear detection system, which converts the charge on the detector into a voltage pulse, which is amplified with shaping and fed to the subsequent measurement part. It is the key component of a nuclear detection system and is widely used in high-energy physics experiments, nuclear diagnostics and so on fields. The whole chip includes a low-noise charge-sensitive preamplifier, a shaper filter and a output driver. Our work will research the single chip integration of this system base on the 0.18 micron CMOS technology. The purpose of this project is to design an ultra-low-power (ULP) SoC and to implement a prototype system for the wireless capsule endoscope which is used for gastrointestinal examination. To make a ULP SoC supplied by a tiny coin battery, a ULP transceiver with 3Mbps TX and 64kbps RX, a wakeup receiver based on wireless energy recovery, a lossless image compressor, an application-optimized MCU, and an on-chip power management unit has been integrated in the SoC. The designed SoC and the prototype system outperforms the conventional work in terms of image resolution, frame rate and battery life.
 
 

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