1. Brief Introduction to Integration Division

Technologies Research Division (abbreviated to Integration Division) is focusing on the research on ULSI integration process, the silicon-based micro/nano meter electronic devices and integration technologies.
The former of the Integration Division is the Integrated Circuit (IC) Process Division. The division has an industrial ULSI process pilot line, which is the first and only IC process line operated by a university in mainland China. The process line consists of complete 5-inch sub-micro CMOS process facilities, including epitaxy, lithography, etching, ion implantation, oxidation, diffusion, thin film sputtering and wafer acceptance test (WAT) equipments and so on, with 960 m2 clean-room. The division is an important part of China’s Northern Microelectronics R&D Base, and is engaged in establishing the Solid-State Devices and Integration Technologies Engineering Research Center of Ministry of Education.
The division now has 13 teaching and research staff, including 1 professor, 10 associate professors and senior engineers, and 2 assistant researchers. In addition, there are 17 laboratory engineers and technicians, and 9 contract research staffs. 
Director: Dr. Liyang Pan
Telephone: 010-62789192
Fax: 010-62771130
Vice-Director: Dr. Jing Wang
Telephone: 010-62789152
Fax: 010-62771130


2. Main R&D fields (Research Interests)
1)      Novel micro/nano-meter materials and electronic devices
         Novel micro/nano-meter materials and high-k dielectric materials
         Strain engineering and high mobility channel engineering for nm-scale devices
         Novel micro/nano-meter devices, process and integration
         SiGe/Ge devices and ICs for extreme environment electronics
2)      Si-based microwave power devices and microwave integrated circuits
          Advanced SiGe epitaxy including selective epitaxy technique
          Microwave power SiGe HBTs and Si-based microwave integrated MMIC
         RF SiGe BiCMOS process technology
         Novel HV and RF power devices and BCD compatible process technologies
3)      Novel non-volatile semiconductor memory devices and integration technologies
         Novel material, device, process and circuits for non-volatile memories
         Non-volatile memories for special applications
         Embedded and novel memories for new applications
        Circuits for Si-based integrated sensors
4)      Novel IC equipments and equipment related process technologies
         IC special equipments common technologies and equipment related process
        SiGe UHV-CVD system and material epitaxy technologies 
        Rapid thermal processing and laser annealing equipments
Main equipments in the IC process line
3. Main R & D Projects
In recent years, the division has undertaken many national priority research projects, such as the National Science and Technology R&D Program, Major National Science & Technology Specific Program, National High-tech R&D Program (863 Program), National Key Basic Research Program (973 Program), National Natural Science Foundation of China, National Development and Reform Commission Industry Specific Program and so on. Moreover, the division has carried out extensive industrial cooperation with oversea and domestic universities, research institutes, and famous semiconductor companies such as Intel, Applied-Material, ASML and Novellus.
The division now undertakes more than 20 research tasks. These tasks consist of the following programs or projects: 2 leading programs from National Key Basic Research Programs, 6 projects from National Natural Science Foundation of China, 3 joint programs from 863 Programs, 1 special issue of “New generation of broadband and networks communication industry” from National Development and Reform Commission, 4 key cooperation projects with domestic research institutions or companies, and 1 international cooperation project. In addition, the division undertakes and initials 6 special issues of Major National Science & Technology Specific Program. Some of these research projects are as follows:
1) Name: Research on low power and high reliable non-volatile memory devices
Sponsor: National Key Basic Research Program of China (973 Program)
 Manager: Jun Xu, Liyang Pan
Duration: 2006-2010
Abstract: Aiming to solve the technical problems and limitations for the traditional scaled non-volatile memory devices, this project mainly researches on the materials, devices and technologies for charge trapping memory, nano-crystal memory and RRAM, which are suitable for next-generation low voltage and low power utilizations.
2) Name: Research on the gate and channel engineering technologies for sub-65nm CMOS devices
Sponsor: National Nature and Science Foundation of China (Key Program)
Manager: Jun Xu
Duration: 2007-2010
 Abstract: This project will focus on the research of new theories and new technologies related to the integration technology of channel and gate engineering, which is based on the new channel materials such as stained silicon, high-k gate dielectric and metal gate electrodes respectively. This research will establish the foundation for developing the VLSI technology with ourselves intellectual property. This project will solve the critical fundamental problems of channel and gate engineering for advance CMOS technology at 65 nm and below generation. Moreover, this project will provide the theoretical and experimental guidance for the realization of next generation high performance CMOS devices and circuits.
3) Name: Study of Power MOSFETs with strained SiGe channel
Sponsor: National Natural Science Foundation of China (Major international cooperation projects)
Manager: Jun Xu, Wei Zhou
Duration: 2009-2011
Abstract: In this project, the process of low voltage power MOSFETs with strained SiGe channel will be studied. The aim of the project is to reduce the Ron of the developed device to improve device performance and save energy. The research contents of the project includes: to study the SiGe epitaxial growth techniques for power MOSFETs; to analyze Ge fraction and doping profile in the channel; to explore the factors which will impact the parameters of the device such as gate dielectric materials and so on; to examine the effects of parasitic BJT on device characteristics; and to investigate the reliability of the developed power MOSFETs.
4) Name: Investigation of buffer Layer for compound semiconductor growth on Si
Sponser: National Natural Science Foundation of China
 Manager: Wei Zhou
 Duration: 2010-2012
 Abstract: Today, the planar silicon process is approaching to its physical limit. The III-V compound semiconductor materials, as candidates of next ULSI materials have been evaluated for the future process development due to their higher electron motilities than silicon. This project will focus on the studies of the process of SiGe/Ge buffer layer which is suitable for III-V compound semiconductor materials grown on silicon wafers.
5) Name: Industrialization of novel power electronic device chip
 Sponsor: National High Technology Research and Development Program (863)
Manager: Zhihong Liu
Duration: 2008-2010
Abstract: Nowadays, power MOSFET and IGBT devices are attracting much attention and experiencing fast evolution in the field of novel power electronic devices. By way of the cooperation with Shanghai Belling Co., Ltd. and Shanghai Integrated Circuit Research & Development Center, the project is concentrated on the technical development of chip design and manufacture, static/dynamic/thermal characteristics tests, reliability and failure analyses. This project will not only realize the industrial production of 200-600V MOSFETs and 600V/1200V IGBTs, but also provide ourselves independent intellectual proprietary for consumer electronics and industry power electronic devices in our country.
6) Name: Materials and technology of Nano-crystal nonvolatile random access memories
Sponsor: National High Tech. Research and Development Program of China
Manager: Zhigang Zhang
Duration: 2008-2010
 Abstract: Based on the characteristics of semiconductor nano-crystal memories and 130nm integrated technology, high density nano-crystal memory arrays will be designed. Being facing with the challenges of low voltage, low power and high velocity operation for the integrated system, many important parameters including circuit velocity, power consumption under low voltage system operation, structure and performance have to be optimized through high voltage switching, multi-channel pre-charging, and new SA-type circuit architecture.
7) Name: Development and industrialization of key RF devices and integrated circuits for TD-SCDMA and LTE TDD base station power amplifier applications
Sponsor: The Program of Industrialization of New Generation Broadband and Network Communications funded by the State Development and Reform Commission, led by Shanghai Belling Co.Ltd.
 Manager: Zhihong Liu and Jun Fu
 Duration: 2010-2011
 Abstract: With evolution of wireless mobile communication systems from 2G to 3G and even 4G, new generation mobile communication systems such as TD-SCDMA and LTE TDD are in the stage of networking and large scale base station deployment. Based on independent research, development and optimization of SiGe and LDMOS technologies, the project is targeted at developing some of the key RF devices and integrated circuit chips suitable for TD-SCDMA and LTE TDD base station applications, and at furthermore realizing industrialization, and at finally promoting building up industry chain of TD-SCDMA and LTE TDD base station power amplifier integrated circuit design, manufacture, and application.
8) Name: Array Architecture and Physical Model for DRAM
Sponsor: the 1st National Key Scientific and Technological Project
 Manager: Liyang Pan, Dong Wu
Duration: 2010-2011
 Abstract: The project mainly researches on the 46nm BWL based array architecture and physical model for 45nm-65nm 1Gb/2Gb DRAM applications.
9) Name: “ULSI IC manufacturing equipment and complete process”
 Sponsor:Major National Science & Technology Specific Program
 Manager: Jun Xu
Duration: 2009-2012
Abstract: In order to fulfill the requirement of high mobility channel at the 22nm technology node, this project will be engaged in the following aspects: to develop new materials including strained Si, Ge, and III-V compound semiconductor and their associated processing technologies; to study the combination and integration technologies with versatile strain processing including SiGe source/drain engineering, Silicon nitride capping layer and so on; to investigate the compatibility and integration technologies of high mobility channel with high-k/metal gate materials; to explore the device performance using Si-based Ge and III-V channel materials; and to develop key process modules for channel engineering. This project will not only provide process modules with ourselves intellectual property, but also will obtain breakthrough in key technologies of the channel engineering for the 22nm technology node. Moreover, this project will provide technical support for the industrialization of the 22nm technology.
10) Name: Research on reliability for 32nm flash devices and circuits
Sponsor: the 2nd National Key Scientific and Technological Project
Manager: Liyang Pan, Zhigang Zhang
Duration: 2009-2011
Abstract: The project mainly research on the reliability for 32nm flash devices and circuits, including the device degradation mechanism and modeling, the improvement techniques of reliable material, device and process, and low CER array for 1Gb memory chip.
11) Name: Research on the Laser Annealing Equipment for Annealing Ultra Shallow Junctions at 32nm technology
 Sponsor: National major science and technology research projects
Manager: Liren Yan
 Duration: 2009-2011
Abstract: The source/drain region moves to the much shallower surface of wafers, as the semiconductor device size shrinks. After implanting dopants into the Si surface, these impurities must be activated via an annealing step. The impurities must not be pushed into deeper substrate so as to form ultra shallow junctions (USJs). Thus the laser anneal technology is used for such a purpose. The project plans to develop a suitable sample machine for the USJ annealing, which can be used for the 32nm node or beyond. We also have planed to build formal laser anneal machines for the IC industry, if the project finishes and successes.
12) Name: A complete set of 0.13mm/0.18mm SiGe BiCMOS process technologies ¾ device modeling, parameter extraction and pilot product design
Sponsor: The 2nd National Key Scientific and Technological Project
Manager: Jun Fu and Zhihong Liu
Duration: 2009-2012
Abstract: Owing to excellent frequency response performance, low noise figure, high linearity and efficiency, SiGe BiCMOS process is becoming a main stream technology for manufacturing RF transceiver and power amplifier, and mm/0.18mm SiGe BiCMOS process technologies, which may comprises the following aspects: to establish a perfect suite of IP libraries and design support systems, to form mass production capacity and application service capability in the field of wireless and optical fiber communication, broadcast television, satellite communication and navigation, radar and internet of things, and to help to create enterprise independent innovation competence and marketing core competitive power. a key technology for manufacturing core chips in new generation communications. The target of the project is to develop 0.13
13) Name: Research on the growth technologies of strained materials on Si substrates
Sponsor: “ULSI IC manufacturing equipment and complete process” Major National Science & Technology Specific Program
Manager: Jing Wang
Duration: 2009-2011
Abstract: Aiming at the process requirement for CMOS devices at 32nm and below generation, this project will develop prospective technologies for novel Si-based substrates. The main research focus of the project is to study the growth techniques of SiGe virtual substrates on bulk Si wafers, and then to achieve strained Si and strained SiGe thin films on the SiGe virtual substrates. Based on the obtained novel Si-based substrates using the new developed growth techniques, the characterization methodologies and application verification test of the strained Si materials will be carried out. The impacts of strain on the device performances will be analyzed. Furthermore, the combination of global and local strain techniques will be explored.
4. Main R&D achievements
The division has made a number of important achievements in the past few years. These achievements involve the following aspects: a complete integration process for 0.35-0.5 micrometer integrated circuits; strained silicon and high mobility channel engineering for nanometer scale CMOS applications; SiGe-HBT microwave power device and MMIC circuits; fast embedded flash memory integration process and IP cores; deep ultraviolet photo-detectors; infrared rapid thermal annealing equipments; UHV-CVD systems for Si/SiGe epitaxy and so on. Some representative achievements have been successfully applied to large scale production. The main achievements in 2010 include:
High speed SiGe HBT planar devices with fT higher than 25GHz have been manufactured successfully by selective and patterned epitaxial techniques. An advanced SiGe HBT process technology with BVCEO>7V,fT>20GHz, and fmax>65GHz have been successfully developed through the cooperation with IC foundry. Insert gain of 15dB and output power at 1dB compression point of 17dBm have been achieved at operation frequency of 1.95GHz for the SiGe HBT darlington MMIC PA chip fabricated by the developed process technology. Since 2009, some RF products based on the above transferred and co-developed SiGe HBT process technologies have been put into mass production in 8-inch line.
Successfully developed an RF LDMOS device with power gain of 14.5dB and output power of 70W at 1dB compression point for 945 MHz operation frequency. These results mark a significant breakthrough in the development of RF LDMOS as one of core microwave power devices for applications in mobile communication base station, broadcast television transmitter, and radar system.
SiGe, strained silicon and high mobility channel engineering have long been engaged in. Ultra-thin relaxed SiGe buffer layers with high Ge content have been fabricated on silicon wafers using low temperature and reduced pressure chemical vapor deposition techniques. High quality strained Ge channel materials have been grown on such virtual substrates using UHV/CVD systems. Furthermore, low temperature selective epitaxy techniques were explored using SiH4/GeH4/HCl as the gas sources, some important parameters were obtained. A research tasks named as “High Mobility Channel Engineering” was charged with as one of the major units. This task was supported by the project of “Pilot research on the key 22-nanometer process technology and platform building”, which was sponsored by the Major National Science and Technology Program of “ultimate-large-scale integrated circuits equipment and complete sets of process”.
 The materials and technology of nano-crystal memories have been systematically studied. Ru-NCNVMs with high performance have been produced through solving the compatibility between Ru NC and semiconductor technology. 8Mbit verification circuit systems have been designed and manufactured based on 130nm integrated technology. The multi-level storage technologies for the charge trapping memory materials are being developed for a long time. The G-bits scale non-volatile flash memories base on 32nm technology are being investigated at the present time.
Based on the research on special application EEPROM/Flash technologies, successfully developed a 256Kbit EEPROM and a 4 Mbit Flash memory.
Research on high precision and low power read-out circuit and ADC array for integrated sensors. The area and power consumption of the ADC is 40m times 915m and 80W, respectively.

High Precision and Low Power Read-out Circuit and ADC Array for Integrated Sensor